Smaller sizes in semiconductor chip fabrication generally lead to corresponding increases in available circuit board real estate and processing speed. Sub-100 nanometer semiconductor technology and methods provide for efficient and fast chip structures, such as circuit lines and gates fabricated on a nanometer-scale; for example, sub-100 nm structures formed through nanolithography patterns may have a lateral dimension between the size of an individual atom and approximately 100 nm.
However, sub-100 nm semiconductor technology presents a number of challenges.
Wherein larger semiconductor structures may be manually designed, sub-100 nanometer processes generally require design engineers to use sophisticated Electronic Design Automation (EDA) tools to convert method and process algorithms directly into circuit structures. And, accordingly, a chip designer must also generally use an EDA tool to confirm chip design manufacturability and acceptable yield optimization.
Design Rule Checking or Check(s) (DRC) refers to EDA determination as to whether a particular chip design satisfies a series of recommended parameters called Design Rules. The main objective of DRC is to achieve a high overall yield and reliability for the design. If design rules are violated, the design may not be functional.
However, conventional chip design techniques may incorporate post-design manufacturing steps outside of the control of the chip designer. Such steps may add extra cost and time to the chip manufacturing process, degrading inductor manufacturing performance and yield beyond that specified or allowable under DRC. Accordingly, computationally intensive DRC routines must be run to verify chip performance and yield during physical verification of the design.
In view of the foregoing, there exists a need for a solution that solves at least one of the deficiencies of the related art.